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#define | COMPILE_FOR_WINDOWS_7 |
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#define | INST_RETIRED_ANY_ADDR (0x309) |
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#define | CPU_CLK_UNHALTED_THREAD_ADDR (0x30A) |
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#define | CPU_CLK_UNHALTED_REF_ADDR (0x30B) |
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#define | IA32_CR_PERF_GLOBAL_CTRL (0x38F) |
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#define | IA32_CR_FIXED_CTR_CTRL (0x38D) |
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#define | IA32_PERFEVTSEL0_ADDR (0x186) |
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#define | IA32_PERFEVTSEL1_ADDR (IA32_PERFEVTSEL0_ADDR + 1) |
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#define | IA32_PERFEVTSEL2_ADDR (IA32_PERFEVTSEL0_ADDR + 2) |
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#define | IA32_PERFEVTSEL3_ADDR (IA32_PERFEVTSEL0_ADDR + 3) |
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#define | PERF_MAX_COUNTERS (7) |
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#define | IA32_DEBUGCTL (0x1D9) |
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#define | IA32_PMC0 (0xC1) |
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#define | IA32_PMC1 (0xC1 + 1) |
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#define | IA32_PMC2 (0xC1 + 2) |
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#define | IA32_PMC3 (0xC1 + 3) |
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#define | MSR_OFFCORE_RSP0 (0x1A6) |
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#define | MSR_OFFCORE_RSP1 (0x1A7) |
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#define | PLATFORM_INFO_ADDR (0xCE) |
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#define | IA32_TIME_STAMP_COUNTER (0x10) |
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#define | MEM_LOAD_RETIRED_L3_MISS_EVTNR (0xCB) |
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#define | MEM_LOAD_RETIRED_L3_MISS_UMASK (0x10) |
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#define | MEM_LOAD_RETIRED_L3_UNSHAREDHIT_EVTNR (0xCB) |
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#define | MEM_LOAD_RETIRED_L3_UNSHAREDHIT_UMASK (0x04) |
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#define | MEM_LOAD_RETIRED_L2_HITM_EVTNR (0xCB) |
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#define | MEM_LOAD_RETIRED_L2_HITM_UMASK (0x08) |
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#define | MEM_LOAD_RETIRED_L2_HIT_EVTNR (0xCB) |
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#define | MEM_LOAD_RETIRED_L2_HIT_UMASK (0x02) |
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#define | MEM_LOAD_UOPS_MISC_RETIRED_LLC_MISS_EVTNR (0xD4) |
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#define | MEM_LOAD_UOPS_MISC_RETIRED_LLC_MISS_UMASK (0x02) |
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#define | MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_NONE_EVTNR (0xD2) |
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#define | MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_NONE_UMASK (0x08) |
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#define | MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_HITM_EVTNR (0xD2) |
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#define | MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_HITM_UMASK (0x04) |
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#define | MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_EVTNR (0xD2) |
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#define | MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_UMASK (0x07) |
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#define | MEM_LOAD_UOPS_RETIRED_L2_HIT_EVTNR (0xD1) |
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#define | MEM_LOAD_UOPS_RETIRED_L2_HIT_UMASK (0x02) |
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#define | ARCH_LLC_REFERENCE_EVTNR (0x2E) |
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#define | ARCH_LLC_REFERENCE_UMASK (0x4F) |
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#define | ARCH_LLC_MISS_EVTNR (0x2E) |
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#define | ARCH_LLC_MISS_UMASK (0x41) |
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#define | ATOM_MEM_LOAD_RETIRED_L2_HIT_EVTNR (0xCB) |
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#define | ATOM_MEM_LOAD_RETIRED_L2_HIT_UMASK (0x01) |
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#define | ATOM_MEM_LOAD_RETIRED_L2_MISS_EVTNR (0xCB) |
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#define | ATOM_MEM_LOAD_RETIRED_L2_MISS_UMASK (0x02) |
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#define | ATOM_MEM_LOAD_RETIRED_L2_HIT_EVTNR (0xCB) |
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#define | ATOM_MEM_LOAD_RETIRED_L2_HIT_UMASK (0x01) |
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#define | ATOM_MEM_LOAD_RETIRED_L2_MISS_EVTNR (0xCB) |
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#define | ATOM_MEM_LOAD_RETIRED_L2_MISS_UMASK (0x02) |
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#define | ATOM_MEM_LOAD_RETIRED_L2_HIT_EVTNR (0xCB) |
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#define | ATOM_MEM_LOAD_RETIRED_L2_HIT_UMASK (0x01) |
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#define | ATOM_MEM_LOAD_RETIRED_L2_MISS_EVTNR (0xCB) |
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#define | ATOM_MEM_LOAD_RETIRED_L2_MISS_UMASK (0x02) |
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#define | MSR_UNCORE_PERF_GLOBAL_CTRL_ADDR (0x391) |
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#define | MSR_UNCORE_PERFEVTSEL0_ADDR (0x3C0) |
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#define | MSR_UNCORE_PERFEVTSEL1_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 1) |
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#define | MSR_UNCORE_PERFEVTSEL2_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 2) |
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#define | MSR_UNCORE_PERFEVTSEL3_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 3) |
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#define | MSR_UNCORE_PERFEVTSEL4_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 4) |
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#define | MSR_UNCORE_PERFEVTSEL5_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 5) |
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#define | MSR_UNCORE_PERFEVTSEL6_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 6) |
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#define | MSR_UNCORE_PERFEVTSEL7_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 7) |
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#define | MSR_UNCORE_PMC0 (0x3B0) |
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#define | MSR_UNCORE_PMC1 (MSR_UNCORE_PMC0 + 1) |
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#define | MSR_UNCORE_PMC2 (MSR_UNCORE_PMC0 + 2) |
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#define | MSR_UNCORE_PMC3 (MSR_UNCORE_PMC0 + 3) |
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#define | MSR_UNCORE_PMC4 (MSR_UNCORE_PMC0 + 4) |
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#define | MSR_UNCORE_PMC5 (MSR_UNCORE_PMC0 + 5) |
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#define | MSR_UNCORE_PMC6 (MSR_UNCORE_PMC0 + 6) |
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#define | MSR_UNCORE_PMC7 (MSR_UNCORE_PMC0 + 7) |
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#define | UNC_QMC_WRITES_FULL_ANY_EVTNR (0x2F) |
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#define | UNC_QMC_WRITES_FULL_ANY_UMASK (0x07) |
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#define | UNC_QMC_NORMAL_READS_ANY_EVTNR (0x2C) |
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#define | UNC_QMC_NORMAL_READS_ANY_UMASK (0x07) |
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#define | UNC_QHL_REQUESTS_EVTNR (0x20) |
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#define | UNC_QHL_REQUESTS_IOH_READS_UMASK (0x01) |
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#define | UNC_QHL_REQUESTS_IOH_WRITES_UMASK (0x02) |
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#define | UNC_QHL_REQUESTS_REMOTE_READS_UMASK (0x04) |
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#define | UNC_QHL_REQUESTS_REMOTE_WRITES_UMASK (0x08) |
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#define | UNC_QHL_REQUESTS_LOCAL_READS_UMASK (0x10) |
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#define | UNC_QHL_REQUESTS_LOCAL_WRITES_UMASK (0x20) |
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#define | U_MSR_PMON_GLOBAL_CTL (0x0C00) |
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#define | MB0_MSR_PERF_GLOBAL_CTL (0x0CA0) |
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#define | MB0_MSR_PMU_CNT_0 (0x0CB1) |
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#define | MB0_MSR_PMU_CNT_CTL_0 (0x0CB0) |
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#define | MB0_MSR_PMU_CNT_1 (0x0CB3) |
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#define | MB0_MSR_PMU_CNT_CTL_1 (0x0CB2) |
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#define | MB0_MSR_PMU_ZDP_CTL_FVC (0x0CAB) |
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#define | MB1_MSR_PERF_GLOBAL_CTL (0x0CE0) |
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#define | MB1_MSR_PMU_CNT_0 (0x0CF1) |
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#define | MB1_MSR_PMU_CNT_CTL_0 (0x0CF0) |
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#define | MB1_MSR_PMU_CNT_1 (0x0CF3) |
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#define | MB1_MSR_PMU_CNT_CTL_1 (0x0CF2) |
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#define | MB1_MSR_PMU_ZDP_CTL_FVC (0x0CEB) |
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#define | BB0_MSR_PERF_GLOBAL_CTL (0x0C20) |
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#define | BB0_MSR_PERF_CNT_1 (0x0C33) |
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#define | BB0_MSR_PERF_CNT_CTL_1 (0x0C32) |
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#define | BB1_MSR_PERF_GLOBAL_CTL (0x0C60) |
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#define | BB1_MSR_PERF_CNT_1 (0x0C73) |
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#define | BB1_MSR_PERF_CNT_CTL_1 (0x0C72) |
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#define | R_MSR_PMON_CTL0 (0x0E10) |
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#define | R_MSR_PMON_CTR0 (0x0E11) |
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#define | R_MSR_PMON_CTL1 (0x0E12) |
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#define | R_MSR_PMON_CTR1 (0x0E13) |
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#define | R_MSR_PMON_CTL2 (0x0E14) |
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#define | R_MSR_PMON_CTR2 (0x0E15) |
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#define | R_MSR_PMON_CTL3 (0x0E16) |
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#define | R_MSR_PMON_CTR3 (0x0E17) |
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#define | R_MSR_PMON_CTL4 (0x0E18) |
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#define | R_MSR_PMON_CTR4 (0x0E19) |
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#define | R_MSR_PMON_CTL5 (0x0E1A) |
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#define | R_MSR_PMON_CTR5 (0x0E1B) |
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#define | R_MSR_PMON_CTL6 (0x0E1C) |
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#define | R_MSR_PMON_CTR6 (0x0E1D) |
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#define | R_MSR_PMON_CTL7 (0x0E1E) |
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#define | R_MSR_PMON_CTR7 (0x0E1F) |
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#define | R_MSR_PMON_CTL8 (0x0E30) |
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#define | R_MSR_PMON_CTR8 (0x0E31) |
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#define | R_MSR_PMON_CTL9 (0x0E32) |
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#define | R_MSR_PMON_CTR9 (0x0E33) |
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#define | R_MSR_PMON_CTL10 (0x0E34) |
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#define | R_MSR_PMON_CTR10 (0x0E35) |
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#define | R_MSR_PMON_CTL11 (0x0E36) |
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#define | R_MSR_PMON_CTR11 (0x0E37) |
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#define | R_MSR_PMON_CTL12 (0x0E38) |
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#define | R_MSR_PMON_CTR12 (0x0E39) |
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#define | R_MSR_PMON_CTL13 (0x0E3A) |
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#define | R_MSR_PMON_CTR13 (0x0E3B) |
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#define | R_MSR_PMON_CTL14 (0x0E3C) |
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#define | R_MSR_PMON_CTR14 (0x0E3D) |
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#define | R_MSR_PMON_CTL15 (0x0E3E) |
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#define | R_MSR_PMON_CTR15 (0x0E3F) |
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#define | R_MSR_PORT0_IPERF_CFG0 (0x0E04) |
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#define | R_MSR_PORT1_IPERF_CFG0 (0x0E05) |
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#define | R_MSR_PORT2_IPERF_CFG0 (0x0E06) |
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#define | R_MSR_PORT3_IPERF_CFG0 (0x0E07) |
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#define | R_MSR_PORT4_IPERF_CFG0 (0x0E08) |
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#define | R_MSR_PORT5_IPERF_CFG0 (0x0E09) |
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#define | R_MSR_PORT6_IPERF_CFG0 (0x0E0A) |
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#define | R_MSR_PORT7_IPERF_CFG0 (0x0E0B) |
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#define | R_MSR_PORT0_IPERF_CFG1 (0x0E24) |
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#define | R_MSR_PORT1_IPERF_CFG1 (0x0E25) |
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#define | R_MSR_PORT2_IPERF_CFG1 (0x0E26) |
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#define | R_MSR_PORT3_IPERF_CFG1 (0x0E27) |
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#define | R_MSR_PORT4_IPERF_CFG1 (0x0E28) |
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#define | R_MSR_PORT5_IPERF_CFG1 (0x0E29) |
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#define | R_MSR_PORT6_IPERF_CFG1 (0x0E2A) |
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#define | R_MSR_PORT7_IPERF_CFG1 (0x0E2B) |
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#define | R_MSR_PMON_GLOBAL_CTL_7_0 (0x0E00) |
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#define | R_MSR_PMON_GLOBAL_CTL_15_8 (0x0E20) |
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#define | W_MSR_PMON_GLOBAL_CTL (0xC80) |
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#define | W_MSR_PMON_FIXED_CTR_CTL (0x395) |
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#define | W_MSR_PMON_FIXED_CTR (0x394) |
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#define | IA32_PQR_ASSOC (0xc8f) |
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#define | IA32_QM_EVTSEL (0xc8d) |
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#define | IA32_QM_CTR (0xc8e) |
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#define | PCM_INVALID_L3_CACHE_OCCUPANCY ((std::numeric_limits<uint64>::max)()) |
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#define | MSR_PKG_ENERGY_STATUS (0x611) |
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#define | MSR_RAPL_POWER_UNIT (0x606) |
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#define | MSR_PKG_POWER_INFO (0x614) |
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#define | PCM_INTEL_PCI_VENDOR_ID (0x8086) |
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#define | PCM_PCI_VENDOR_ID_OFFSET (0) |
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#define | JKTIVT_MC0_CH0_REGISTER_DEV_ADDR (16) |
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#define | JKTIVT_MC0_CH1_REGISTER_DEV_ADDR (16) |
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#define | JKTIVT_MC0_CH2_REGISTER_DEV_ADDR (16) |
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#define | JKTIVT_MC0_CH3_REGISTER_DEV_ADDR (16) |
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#define | JKTIVT_MC0_CH0_REGISTER_FUNC_ADDR (4) |
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#define | JKTIVT_MC0_CH1_REGISTER_FUNC_ADDR (5) |
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#define | JKTIVT_MC0_CH2_REGISTER_FUNC_ADDR (0) |
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#define | JKTIVT_MC0_CH3_REGISTER_FUNC_ADDR (1) |
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#define | JKTIVT_MC1_CH0_REGISTER_DEV_ADDR (30) |
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#define | JKTIVT_MC1_CH1_REGISTER_DEV_ADDR (30) |
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#define | JKTIVT_MC1_CH2_REGISTER_DEV_ADDR (30) |
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#define | JKTIVT_MC1_CH3_REGISTER_DEV_ADDR (30) |
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#define | JKTIVT_MC1_CH0_REGISTER_FUNC_ADDR (4) |
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#define | JKTIVT_MC1_CH1_REGISTER_FUNC_ADDR (5) |
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#define | JKTIVT_MC1_CH2_REGISTER_FUNC_ADDR (0) |
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#define | JKTIVT_MC1_CH3_REGISTER_FUNC_ADDR (1) |
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#define | HSX_MC0_CH0_REGISTER_DEV_ADDR (20) |
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#define | HSX_MC0_CH1_REGISTER_DEV_ADDR (20) |
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#define | HSX_MC0_CH2_REGISTER_DEV_ADDR (21) |
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#define | HSX_MC0_CH3_REGISTER_DEV_ADDR (21) |
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#define | HSX_MC0_CH0_REGISTER_FUNC_ADDR (0) |
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#define | HSX_MC0_CH1_REGISTER_FUNC_ADDR (1) |
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#define | HSX_MC0_CH2_REGISTER_FUNC_ADDR (0) |
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#define | HSX_MC0_CH3_REGISTER_FUNC_ADDR (1) |
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#define | HSX_MC1_CH0_REGISTER_DEV_ADDR (23) |
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#define | HSX_MC1_CH1_REGISTER_DEV_ADDR (23) |
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#define | HSX_MC1_CH2_REGISTER_DEV_ADDR (24) |
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#define | HSX_MC1_CH3_REGISTER_DEV_ADDR (24) |
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#define | HSX_MC1_CH0_REGISTER_FUNC_ADDR (0) |
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#define | HSX_MC1_CH1_REGISTER_FUNC_ADDR (1) |
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#define | HSX_MC1_CH2_REGISTER_FUNC_ADDR (0) |
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#define | HSX_MC1_CH3_REGISTER_FUNC_ADDR (1) |
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#define | MC_CH_PCI_PMON_BOX_CTL_ADDR (0x0F4) |
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#define | MC_CH_PCI_PMON_FIXED_CTL_ADDR (0x0F0) |
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#define | MC_CH_PCI_PMON_CTL3_ADDR (0x0E4) |
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#define | MC_CH_PCI_PMON_CTL2_ADDR (0x0E0) |
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#define | MC_CH_PCI_PMON_CTL1_ADDR (0x0DC) |
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#define | MC_CH_PCI_PMON_CTL0_ADDR (0x0D8) |
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#define | MC_CH_PCI_PMON_FIXED_CTR_ADDR (0x0D0) |
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#define | MC_CH_PCI_PMON_CTR3_ADDR (0x0B8) |
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#define | MC_CH_PCI_PMON_CTR2_ADDR (0x0B0) |
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#define | MC_CH_PCI_PMON_CTR1_ADDR (0x0A8) |
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#define | MC_CH_PCI_PMON_CTR0_ADDR (0x0A0) |
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#define | JKTIVT_QPI_PORT0_REGISTER_DEV_ADDR (8) |
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#define | JKTIVT_QPI_PORT0_REGISTER_FUNC_ADDR (2) |
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#define | JKTIVT_QPI_PORT1_REGISTER_DEV_ADDR (9) |
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#define | JKTIVT_QPI_PORT1_REGISTER_FUNC_ADDR (2) |
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#define | JKTIVT_QPI_PORT2_REGISTER_DEV_ADDR (24) |
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#define | JKTIVT_QPI_PORT2_REGISTER_FUNC_ADDR (2) |
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#define | HSX_QPI_PORT0_REGISTER_DEV_ADDR (8) |
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#define | HSX_QPI_PORT0_REGISTER_FUNC_ADDR (2) |
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#define | HSX_QPI_PORT1_REGISTER_DEV_ADDR (9) |
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#define | HSX_QPI_PORT1_REGISTER_FUNC_ADDR (2) |
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#define | HSX_QPI_PORT2_REGISTER_DEV_ADDR (10) |
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#define | HSX_QPI_PORT2_REGISTER_FUNC_ADDR (2) |
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#define | QPI_PORT0_MISC_REGISTER_FUNC_ADDR (0) |
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#define | QPI_PORT1_MISC_REGISTER_FUNC_ADDR (0) |
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#define | QPI_PORT2_MISC_REGISTER_FUNC_ADDR (0) |
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#define | Q_P_PCI_PMON_BOX_CTL_ADDR (0x0F4) |
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#define | Q_P_PCI_PMON_CTL3_ADDR (0x0E4) |
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#define | Q_P_PCI_PMON_CTL2_ADDR (0x0E0) |
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#define | Q_P_PCI_PMON_CTL1_ADDR (0x0DC) |
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#define | Q_P_PCI_PMON_CTL0_ADDR (0x0D8) |
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#define | Q_P_PCI_PMON_CTR3_ADDR (0x0B8) |
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#define | Q_P_PCI_PMON_CTR2_ADDR (0x0B0) |
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#define | Q_P_PCI_PMON_CTR1_ADDR (0x0A8) |
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#define | Q_P_PCI_PMON_CTR0_ADDR (0x0A0) |
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#define | QPI_RATE_STATUS_ADDR (0x0D4) |
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#define | JKTIVT_PCU_MSR_PMON_CTR3_ADDR (0x0C39) |
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#define | JKTIVT_PCU_MSR_PMON_CTR2_ADDR (0x0C38) |
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#define | JKTIVT_PCU_MSR_PMON_CTR1_ADDR (0x0C37) |
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#define | JKTIVT_PCU_MSR_PMON_CTR0_ADDR (0x0C36) |
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#define | JKTIVT_PCU_MSR_PMON_BOX_FILTER_ADDR (0x0C34) |
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#define | JKTIVT_PCU_MSR_PMON_CTL3_ADDR (0x0C33) |
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#define | JKTIVT_PCU_MSR_PMON_CTL2_ADDR (0x0C32) |
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#define | JKTIVT_PCU_MSR_PMON_CTL1_ADDR (0x0C31) |
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#define | JKTIVT_PCU_MSR_PMON_CTL0_ADDR (0x0C30) |
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#define | JKTIVT_PCU_MSR_PMON_BOX_CTL_ADDR (0x0C24) |
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#define | HSX_PCU_MSR_PMON_CTR3_ADDR (0x071A) |
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#define | HSX_PCU_MSR_PMON_CTR2_ADDR (0x0719) |
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#define | HSX_PCU_MSR_PMON_CTR1_ADDR (0x0718) |
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#define | HSX_PCU_MSR_PMON_CTR0_ADDR (0x0717) |
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#define | HSX_PCU_MSR_PMON_BOX_FILTER_ADDR (0x0715) |
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#define | HSX_PCU_MSR_PMON_CTL3_ADDR (0x0714) |
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#define | HSX_PCU_MSR_PMON_CTL2_ADDR (0x0713) |
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#define | HSX_PCU_MSR_PMON_CTL1_ADDR (0x0712) |
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#define | HSX_PCU_MSR_PMON_CTL0_ADDR (0x0711) |
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#define | HSX_PCU_MSR_PMON_BOX_CTL_ADDR (0x0710) |
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#define | MC_CH_PCI_PMON_BOX_CTL_RST_CONTROL (1<<0) |
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#define | MC_CH_PCI_PMON_BOX_CTL_RST_COUNTERS (1<<1) |
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#define | MC_CH_PCI_PMON_BOX_CTL_FRZ (1<<8) |
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#define | MC_CH_PCI_PMON_BOX_CTL_FRZ_EN (1<<16) |
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#define | UNCORE_PMON_BOX_CTL_VALID_BITS_MASK ((1<<17)-1) |
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#define | MC_CH_PCI_PMON_FIXED_CTL_RST (1<<19) |
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#define | MC_CH_PCI_PMON_FIXED_CTL_EN (1<<22) |
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#define | MC_CH_PCI_PMON_CTL_EVENT(x) (x<<0) |
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#define | MC_CH_PCI_PMON_CTL_UMASK(x) (x<<8) |
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#define | MC_CH_PCI_PMON_CTL_RST (1<<17) |
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#define | MC_CH_PCI_PMON_CTL_EDGE_DET (1<<18) |
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#define | MC_CH_PCI_PMON_CTL_EN (1<<22) |
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#define | MC_CH_PCI_PMON_CTL_INVERT (1<<23) |
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#define | MC_CH_PCI_PMON_CTL_THRESH(x) (x<<24UL) |
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#define | Q_P_PCI_PMON_BOX_CTL_RST_CONTROL (1<<0) |
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#define | Q_P_PCI_PMON_BOX_CTL_RST_COUNTERS (1<<1) |
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#define | Q_P_PCI_PMON_BOX_CTL_RST_FRZ (1<<8) |
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#define | Q_P_PCI_PMON_BOX_CTL_RST_FRZ_EN (1<<16) |
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#define | Q_P_PCI_PMON_CTL_EVENT(x) (x<<0) |
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#define | Q_P_PCI_PMON_CTL_UMASK(x) (x<<8) |
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#define | Q_P_PCI_PMON_CTL_RST (1<<17) |
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#define | Q_P_PCI_PMON_CTL_EDGE_DET (1<<18) |
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#define | Q_P_PCI_PMON_CTL_EVENT_EXT (1<<21) |
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#define | Q_P_PCI_PMON_CTL_EN (1<<22) |
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#define | Q_P_PCI_PMON_CTL_INVERT (1<<23) |
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#define | Q_P_PCI_PMON_CTL_THRESH(x) (x<<24UL) |
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#define | PCU_MSR_PMON_BOX_FILTER_BAND_0(x) (x<<0) |
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#define | PCU_MSR_PMON_BOX_FILTER_BAND_1(x) (x<<8) |
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#define | PCU_MSR_PMON_BOX_FILTER_BAND_2(x) (x<<16) |
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#define | PCU_MSR_PMON_BOX_FILTER_BAND_3(x) (x<<24) |
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#define | PCU_MSR_PMON_BOX_CTL_RST_CONTROL (1<<0) |
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#define | PCU_MSR_PMON_BOX_CTL_RST_COUNTERS (1<<1) |
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#define | PCU_MSR_PMON_BOX_CTL_FRZ (1<<8) |
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#define | PCU_MSR_PMON_BOX_CTL_FRZ_EN (1<<16) |
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#define | PCU_MSR_PMON_CTL_EVENT(x) (x<<0) |
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#define | PCU_MSR_PMON_CTL_OCC_SEL(x) (x<<14) |
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#define | PCU_MSR_PMON_CTL_RST (1<<17) |
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#define | PCU_MSR_PMON_CTL_EDGE_DET (1<<18) |
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#define | PCU_MSR_PMON_CTL_EXTRA_SEL (1<<21) |
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#define | PCU_MSR_PMON_CTL_EN (1<<22) |
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#define | PCU_MSR_PMON_CTL_INVERT (1<<23) |
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#define | PCU_MSR_PMON_CTL_THRESH(x) (x<<24UL) |
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#define | PCU_MSR_PMON_CTL_OCC_INVERT (1UL<<30UL) |
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#define | PCU_MSR_PMON_CTL_OCC_EDGE_DET (1UL<<31UL) |
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#define | JKT_C0_MSR_PMON_CTR3 0x0D19 |
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#define | JKT_C0_MSR_PMON_CTR2 0x0D18 |
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#define | JKT_C0_MSR_PMON_CTR1 0x0D17 |
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#define | JKT_C0_MSR_PMON_CTR0 0x0D16 |
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#define | JKT_C0_MSR_PMON_BOX_FILTER 0x0D14 |
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#define | JKT_C0_MSR_PMON_CTL3 0x0D13 |
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#define | JKT_C0_MSR_PMON_CTL2 0x0D12 |
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#define | JKT_C0_MSR_PMON_CTL1 0x0D11 |
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#define | JKT_C0_MSR_PMON_CTL0 0x0D10 |
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#define | JKT_C0_MSR_PMON_BOX_CTL 0x0D04 |
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#define | JKTIVT_CBO_MSR_STEP 0x0020 |
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#define | IVT_C0_MSR_PMON_BOX_FILTER1 0x0D1A |
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#define | HSX_C0_MSR_PMON_CTR3 0x0E0B |
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#define | HSX_C0_MSR_PMON_CTR2 0x0E0A |
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#define | HSX_C0_MSR_PMON_CTR1 0x0E09 |
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#define | HSX_C0_MSR_PMON_CTR0 0x0E08 |
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#define | HSX_C0_MSR_PMON_BOX_FILTER1 0x0E06 |
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#define | HSX_C0_MSR_PMON_BOX_FILTER 0x0E05 |
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#define | HSX_C0_MSR_PMON_CTL3 0x0E04 |
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#define | HSX_C0_MSR_PMON_CTL2 0x0E03 |
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#define | HSX_C0_MSR_PMON_CTL1 0x0E02 |
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#define | HSX_C0_MSR_PMON_CTL0 0x0E01 |
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#define | HSX_C0_MSR_PMON_BOX_STATUS 0x0E07 |
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#define | HSX_C0_MSR_PMON_BOX_CTL 0x0E00 |
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#define | HSX_CBO_MSR_STEP 0x0010 |
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#define | CBO_MSR_PMON_BOX_CTL_RST_CONTROL (1<<0) |
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#define | CBO_MSR_PMON_BOX_CTL_RST_COUNTERS (1<<1) |
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#define | CBO_MSR_PMON_BOX_CTL_FRZ (1<<8) |
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#define | CBO_MSR_PMON_BOX_CTL_FRZ_EN (1<<16) |
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#define | CBO_MSR_PMON_CTL_EVENT(x) (x<<0) |
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#define | CBO_MSR_PMON_CTL_UMASK(x) (x<<8) |
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#define | CBO_MSR_PMON_CTL_RST (1<<17) |
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#define | CBO_MSR_PMON_CTL_EDGE_DET (1<<18) |
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#define | CBO_MSR_PMON_CTL_TID_EN (1<<19) |
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#define | CBO_MSR_PMON_CTL_EN (1<<22) |
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#define | CBO_MSR_PMON_CTL_INVERT (1<<23) |
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#define | CBO_MSR_PMON_CTL_THRESH(x) (x<<24UL) |
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#define | JKT_CBO_MSR_PMON_BOX_FILTER_OPC(x) (x<<23UL) |
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#define | IVTHSX_CBO_MSR_PMON_BOX_FILTER1_OPC(x) (x<<20UL) |
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#define | MSR_PACKAGE_THERM_STATUS (0x01B1) |
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#define | MSR_IA32_THERM_STATUS (0x019C) |
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#define | PCM_INVALID_THERMAL_HEADROOM ((std::numeric_limits<int32>::min)()) |
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#define | MSR_DRAM_ENERGY_STATUS (0x0619) |
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#define | MSR_PKG_C2_RESIDENCY (0x60D) |
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#define | MSR_PKG_C3_RESIDENCY (0x3F8) |
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#define | MSR_PKG_C6_RESIDENCY (0x3F9) |
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#define | MSR_PKG_C7_RESIDENCY (0x3FA) |
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#define | MSR_CORE_C3_RESIDENCY (0x3FC) |
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#define | MSR_CORE_C6_RESIDENCY (0x3FD) |
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#define | MSR_CORE_C7_RESIDENCY (0x3FE) |
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