Intel(r) Performance Counter Monitor
types.h
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1 /*
2 Copyright (c) 2009-2013, Intel Corporation
3 All rights reserved.
4 
5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
6 
7  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
8  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
9  * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
10 
11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12 */
13 // written by Roman Dementiev
14 //
15 
16 #ifndef CPUCounters_TYPES_H
17 #define CPUCounters_TYPES_H
18 
19 
24 // compile for Windows 7 or Windows Server 2008 R2 (processor group support needed for systems with high core count)
25 #define COMPILE_FOR_WINDOWS_7
26 
27 #undef PCM_DEBUG
28 
29 #include <iostream>
30 #include <istream>
31 #include <sstream>
32 #include <iomanip>
33 
34 typedef unsigned long long uint64;
35 typedef signed long long int64;
36 typedef unsigned int uint32;
37 typedef signed int int32;
38 
39 
40 /*
41  MSR addreses from
42  "Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B:
43  System Programming Guide, Part 2", Appendix A "PERFORMANCE-MONITORING EVENTS"
44 */
45 
46 #define INST_RETIRED_ANY_ADDR (0x309)
47 #define CPU_CLK_UNHALTED_THREAD_ADDR (0x30A)
48 #define CPU_CLK_UNHALTED_REF_ADDR (0x30B)
49 #define IA32_CR_PERF_GLOBAL_CTRL (0x38F)
50 #define IA32_CR_FIXED_CTR_CTRL (0x38D)
51 #define IA32_PERFEVTSEL0_ADDR (0x186)
52 #define IA32_PERFEVTSEL1_ADDR (IA32_PERFEVTSEL0_ADDR + 1)
53 #define IA32_PERFEVTSEL2_ADDR (IA32_PERFEVTSEL0_ADDR + 2)
54 #define IA32_PERFEVTSEL3_ADDR (IA32_PERFEVTSEL0_ADDR + 3)
55 
56 #define PERF_MAX_COUNTERS (7)
57 
58 #define IA32_DEBUGCTL (0x1D9)
59 
60 #define IA32_PMC0 (0xC1)
61 #define IA32_PMC1 (0xC1 + 1)
62 #define IA32_PMC2 (0xC1 + 2)
63 #define IA32_PMC3 (0xC1 + 3)
64 
65 #define MSR_OFFCORE_RSP0 (0x1A6)
66 #define MSR_OFFCORE_RSP1 (0x1A7)
67 
68 /* From Table B-5. of the above mentioned document */
69 #define PLATFORM_INFO_ADDR (0xCE)
70 
71 #define IA32_TIME_STAMP_COUNTER (0x10)
72 
73 // Event IDs
74 
75 // Nehalem/Westmere on-core events
76 #define MEM_LOAD_RETIRED_L3_MISS_EVTNR (0xCB)
77 #define MEM_LOAD_RETIRED_L3_MISS_UMASK (0x10)
78 
79 #define MEM_LOAD_RETIRED_L3_UNSHAREDHIT_EVTNR (0xCB)
80 #define MEM_LOAD_RETIRED_L3_UNSHAREDHIT_UMASK (0x04)
81 
82 #define MEM_LOAD_RETIRED_L2_HITM_EVTNR (0xCB)
83 #define MEM_LOAD_RETIRED_L2_HITM_UMASK (0x08)
84 
85 #define MEM_LOAD_RETIRED_L2_HIT_EVTNR (0xCB)
86 #define MEM_LOAD_RETIRED_L2_HIT_UMASK (0x02)
87 
88 // Sandy Bridge on-core events
89 
90 #define MEM_LOAD_UOPS_MISC_RETIRED_LLC_MISS_EVTNR (0xD4)
91 #define MEM_LOAD_UOPS_MISC_RETIRED_LLC_MISS_UMASK (0x02)
92 
93 #define MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_NONE_EVTNR (0xD2)
94 #define MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_NONE_UMASK (0x08)
95 
96 #define MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_HITM_EVTNR (0xD2)
97 #define MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_HITM_UMASK (0x04)
98 
99 #define MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_EVTNR (0xD2)
100 #define MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_UMASK (0x07)
101 
102 #define MEM_LOAD_UOPS_RETIRED_L2_HIT_EVTNR (0xD1)
103 #define MEM_LOAD_UOPS_RETIRED_L2_HIT_UMASK (0x02)
104 
105 // architectural on-core events
106 
107 #define ARCH_LLC_REFERENCE_EVTNR (0x2E)
108 #define ARCH_LLC_REFERENCE_UMASK (0x4F)
109 
110 #define ARCH_LLC_MISS_EVTNR (0x2E)
111 #define ARCH_LLC_MISS_UMASK (0x41)
112 
113 // Atom on-core events
114 
115 #define ATOM_MEM_LOAD_RETIRED_L2_HIT_EVTNR (0xCB)
116 #define ATOM_MEM_LOAD_RETIRED_L2_HIT_UMASK (0x01)
117 
118 #define ATOM_MEM_LOAD_RETIRED_L2_MISS_EVTNR (0xCB)
119 #define ATOM_MEM_LOAD_RETIRED_L2_MISS_UMASK (0x02)
120 
121 #define ATOM_MEM_LOAD_RETIRED_L2_HIT_EVTNR (0xCB)
122 #define ATOM_MEM_LOAD_RETIRED_L2_HIT_UMASK (0x01)
123 
124 #define ATOM_MEM_LOAD_RETIRED_L2_MISS_EVTNR (0xCB)
125 #define ATOM_MEM_LOAD_RETIRED_L2_MISS_UMASK (0x02)
126 
127 #define ATOM_MEM_LOAD_RETIRED_L2_HIT_EVTNR (0xCB)
128 #define ATOM_MEM_LOAD_RETIRED_L2_HIT_UMASK (0x01)
129 
130 #define ATOM_MEM_LOAD_RETIRED_L2_MISS_EVTNR (0xCB)
131 #define ATOM_MEM_LOAD_RETIRED_L2_MISS_UMASK (0x02)
132 
133 /*
134  For Nehalem(-EP) processors from Intel(r) 64 and IA-32 Architectures Software Developer's Manual
135 */
136 
137 // Uncore msrs
138 
139 #define MSR_UNCORE_PERF_GLOBAL_CTRL_ADDR (0x391)
140 
141 #define MSR_UNCORE_PERFEVTSEL0_ADDR (0x3C0)
142 #define MSR_UNCORE_PERFEVTSEL1_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 1)
143 #define MSR_UNCORE_PERFEVTSEL2_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 2)
144 #define MSR_UNCORE_PERFEVTSEL3_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 3)
145 #define MSR_UNCORE_PERFEVTSEL4_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 4)
146 #define MSR_UNCORE_PERFEVTSEL5_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 5)
147 #define MSR_UNCORE_PERFEVTSEL6_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 6)
148 #define MSR_UNCORE_PERFEVTSEL7_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 7)
149 
150 
151 #define MSR_UNCORE_PMC0 (0x3B0)
152 #define MSR_UNCORE_PMC1 (MSR_UNCORE_PMC0 + 1)
153 #define MSR_UNCORE_PMC2 (MSR_UNCORE_PMC0 + 2)
154 #define MSR_UNCORE_PMC3 (MSR_UNCORE_PMC0 + 3)
155 #define MSR_UNCORE_PMC4 (MSR_UNCORE_PMC0 + 4)
156 #define MSR_UNCORE_PMC5 (MSR_UNCORE_PMC0 + 5)
157 #define MSR_UNCORE_PMC6 (MSR_UNCORE_PMC0 + 6)
158 #define MSR_UNCORE_PMC7 (MSR_UNCORE_PMC0 + 7)
159 
160 // Uncore event IDs
161 
162 #define UNC_QMC_WRITES_FULL_ANY_EVTNR (0x2F)
163 #define UNC_QMC_WRITES_FULL_ANY_UMASK (0x07)
164 
165 #define UNC_QMC_NORMAL_READS_ANY_EVTNR (0x2C)
166 #define UNC_QMC_NORMAL_READS_ANY_UMASK (0x07)
167 
168 #define UNC_QHL_REQUESTS_EVTNR (0x20)
169 
170 #define UNC_QHL_REQUESTS_IOH_READS_UMASK (0x01)
171 #define UNC_QHL_REQUESTS_IOH_WRITES_UMASK (0x02)
172 #define UNC_QHL_REQUESTS_REMOTE_READS_UMASK (0x04)
173 #define UNC_QHL_REQUESTS_REMOTE_WRITES_UMASK (0x08)
174 #define UNC_QHL_REQUESTS_LOCAL_READS_UMASK (0x10)
175 #define UNC_QHL_REQUESTS_LOCAL_WRITES_UMASK (0x20)
176 
177 /*
178  From "Intel(r) Xeon(r) Processor 7500 Series Uncore Programming Guide"
179 */
180 
181 // Beckton uncore event IDs
182 
183 #define U_MSR_PMON_GLOBAL_CTL (0x0C00)
184 
185 #define MB0_MSR_PERF_GLOBAL_CTL (0x0CA0)
186 #define MB0_MSR_PMU_CNT_0 (0x0CB1)
187 #define MB0_MSR_PMU_CNT_CTL_0 (0x0CB0)
188 #define MB0_MSR_PMU_CNT_1 (0x0CB3)
189 #define MB0_MSR_PMU_CNT_CTL_1 (0x0CB2)
190 #define MB0_MSR_PMU_ZDP_CTL_FVC (0x0CAB)
191 
192 
193 #define MB1_MSR_PERF_GLOBAL_CTL (0x0CE0)
194 #define MB1_MSR_PMU_CNT_0 (0x0CF1)
195 #define MB1_MSR_PMU_CNT_CTL_0 (0x0CF0)
196 #define MB1_MSR_PMU_CNT_1 (0x0CF3)
197 #define MB1_MSR_PMU_CNT_CTL_1 (0x0CF2)
198 #define MB1_MSR_PMU_ZDP_CTL_FVC (0x0CEB)
199 
200 #define BB0_MSR_PERF_GLOBAL_CTL (0x0C20)
201 #define BB0_MSR_PERF_CNT_1 (0x0C33)
202 #define BB0_MSR_PERF_CNT_CTL_1 (0x0C32)
203 
204 #define BB1_MSR_PERF_GLOBAL_CTL (0x0C60)
205 #define BB1_MSR_PERF_CNT_1 (0x0C73)
206 #define BB1_MSR_PERF_CNT_CTL_1 (0x0C72)
207 
208 #define R_MSR_PMON_CTL0 (0x0E10)
209 #define R_MSR_PMON_CTR0 (0x0E11)
210 #define R_MSR_PMON_CTL1 (0x0E12)
211 #define R_MSR_PMON_CTR1 (0x0E13)
212 #define R_MSR_PMON_CTL2 (0x0E14)
213 #define R_MSR_PMON_CTR2 (0x0E15)
214 #define R_MSR_PMON_CTL3 (0x0E16)
215 #define R_MSR_PMON_CTR3 (0x0E17)
216 #define R_MSR_PMON_CTL4 (0x0E18)
217 #define R_MSR_PMON_CTR4 (0x0E19)
218 #define R_MSR_PMON_CTL5 (0x0E1A)
219 #define R_MSR_PMON_CTR5 (0x0E1B)
220 #define R_MSR_PMON_CTL6 (0x0E1C)
221 #define R_MSR_PMON_CTR6 (0x0E1D)
222 #define R_MSR_PMON_CTL7 (0x0E1E)
223 #define R_MSR_PMON_CTR7 (0x0E1F)
224 #define R_MSR_PMON_CTL8 (0x0E30)
225 #define R_MSR_PMON_CTR8 (0x0E31)
226 #define R_MSR_PMON_CTL9 (0x0E32)
227 #define R_MSR_PMON_CTR9 (0x0E33)
228 #define R_MSR_PMON_CTL10 (0x0E34)
229 #define R_MSR_PMON_CTR10 (0x0E35)
230 #define R_MSR_PMON_CTL11 (0x0E36)
231 #define R_MSR_PMON_CTR11 (0x0E37)
232 #define R_MSR_PMON_CTL12 (0x0E38)
233 #define R_MSR_PMON_CTR12 (0x0E39)
234 #define R_MSR_PMON_CTL13 (0x0E3A)
235 #define R_MSR_PMON_CTR13 (0x0E3B)
236 #define R_MSR_PMON_CTL14 (0x0E3C)
237 #define R_MSR_PMON_CTR14 (0x0E3D)
238 #define R_MSR_PMON_CTL15 (0x0E3E)
239 #define R_MSR_PMON_CTR15 (0x0E3F)
240 
241 #define R_MSR_PORT0_IPERF_CFG0 (0x0E04)
242 #define R_MSR_PORT1_IPERF_CFG0 (0x0E05)
243 #define R_MSR_PORT2_IPERF_CFG0 (0x0E06)
244 #define R_MSR_PORT3_IPERF_CFG0 (0x0E07)
245 #define R_MSR_PORT4_IPERF_CFG0 (0x0E08)
246 #define R_MSR_PORT5_IPERF_CFG0 (0x0E09)
247 #define R_MSR_PORT6_IPERF_CFG0 (0x0E0A)
248 #define R_MSR_PORT7_IPERF_CFG0 (0x0E0B)
249 
250 #define R_MSR_PORT0_IPERF_CFG1 (0x0E24)
251 #define R_MSR_PORT1_IPERF_CFG1 (0x0E25)
252 #define R_MSR_PORT2_IPERF_CFG1 (0x0E26)
253 #define R_MSR_PORT3_IPERF_CFG1 (0x0E27)
254 #define R_MSR_PORT4_IPERF_CFG1 (0x0E28)
255 #define R_MSR_PORT5_IPERF_CFG1 (0x0E29)
256 #define R_MSR_PORT6_IPERF_CFG1 (0x0E2A)
257 #define R_MSR_PORT7_IPERF_CFG1 (0x0E2B)
258 
259 #define R_MSR_PMON_GLOBAL_CTL_7_0 (0x0E00)
260 #define R_MSR_PMON_GLOBAL_CTL_15_8 (0x0E20)
261 
262 #define W_MSR_PMON_GLOBAL_CTL (0xC80)
263 #define W_MSR_PMON_FIXED_CTR_CTL (0x395)
264 #define W_MSR_PMON_FIXED_CTR (0x394)
265 
266 /*
267  * Platform QoS MSRs
268  */
269 
270 #define IA32_PQR_ASSOC (0xc8f)
271 #define IA32_QM_EVTSEL (0xc8d)
272 #define IA32_QM_CTR (0xc8e)
273 
274 #define PCM_INVALID_L3_CACHE_OCCUPANCY ((std::numeric_limits<uint64>::max)())
275 
276 /* \brief Event Select Register format
277 
278  According to
279  "Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B:
280  System Programming Guide, Part 2", Figure 30-6. Layout of IA32_PERFEVTSELx
281  MSRs Supporting Architectural Performance Monitoring Version 3
282 */
284 {
285  union
286  {
287  struct
288  {
289  uint64 event_select : 8;
290  uint64 umask : 8;
291  uint64 usr : 1;
292  uint64 os : 1;
293  uint64 edge : 1;
294  uint64 pin_control : 1;
295  uint64 apic_int : 1;
296  uint64 any_thread : 1;
297  uint64 enable : 1;
298  uint64 invert : 1;
299  uint64 cmask : 8;
300  uint64 in_tx : 1;
301  uint64 in_txcp : 1;
302  uint64 reservedX : 30;
303  } fields;
304  uint64 value;
305  };
306 };
307 
308 
309 /* \brief Fixed Event Control Register format
310 
311  According to
312  "Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B:
313  System Programming Guide, Part 2", Figure 30-7. Layout of
314  IA32_FIXED_CTR_CTRL MSR Supporting Architectural Performance Monitoring Version 3
315 */
317 {
318  union
319  {
320  struct
321  {
322  // CTR0
323  uint64 os0 : 1;
324  uint64 usr0 : 1;
325  uint64 any_thread0 : 1;
326  uint64 enable_pmi0 : 1;
327  // CTR1
328  uint64 os1 : 1;
329  uint64 usr1 : 1;
330  uint64 any_thread1 : 1;
331  uint64 enable_pmi1 : 1;
332  // CTR2
333  uint64 os2 : 1;
334  uint64 usr2 : 1;
335  uint64 any_thread2 : 1;
336  uint64 enable_pmi2 : 1;
337 
338  uint64 reserved1 : 52;
339  } fields;
340  uint64 value;
341  };
342 };
343 
344 inline std::ostream & operator << (std::ostream & o, const FixedEventControlRegister & reg)
345 {
346  o << "os0\t\t" << reg.fields.os0 << std::endl;
347  o << "usr0\t\t" << reg.fields.usr0 << std::endl;
348  o << "any_thread0\t" << reg.fields.any_thread0 << std::endl;
349  o << "enable_pmi0\t" << reg.fields.enable_pmi0 << std::endl;
350 
351  o << "os1\t\t" << reg.fields.os1 << std::endl;
352  o << "usr1\t\t" << reg.fields.usr1 << std::endl;
353  o << "any_thread1\t" << reg.fields.any_thread1 << std::endl;
354  o << "enable_pmi10\t" << reg.fields.enable_pmi1 << std::endl;
355 
356  o << "os2\t\t" << reg.fields.os2 << std::endl;
357  o << "usr2\t\t" << reg.fields.usr2 << std::endl;
358  o << "any_thread2\t" << reg.fields.any_thread2 << std::endl;
359  o << "enable_pmi2\t" << reg.fields.enable_pmi2 << std::endl;
360 
361  o << "reserved1\t" << reg.fields.reserved1 << std::endl;
362  return o;
363 }
364 
365 // UNCORE COUNTER CONTROL
366 
367 /* \brief Uncore Event Select Register Register format
368 
369  According to
370  "Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B:
371  System Programming Guide, Part 2", Figure 30-20. Layout of MSR_UNCORE_PERFEVTSELx MSRs
372 */
374 {
375  union
376  {
377  struct
378  {
379  uint64 event_select : 8;
380  uint64 umask : 8;
381  uint64 reserved1 : 1;
382  uint64 occ_ctr_rst : 1;
383  uint64 edge : 1;
384  uint64 reserved2 : 1;
385  uint64 enable_pmi : 1;
386  uint64 reserved3 : 1;
387  uint64 enable : 1;
388  uint64 invert : 1;
389  uint64 cmask : 8;
390  uint64 reservedx : 32;
391  } fields;
392  uint64 value;
393  };
394 };
395 
396 /* \brief Beckton Uncore PMU ZDP FVC Control Register format
397 
398  From "Intel(r) Xeon(r) Processor 7500 Series Uncore Programming Guide"
399  Table 2-80. M_MSR_PMU_ZDP_CTL_FVC Register - Field Definitions
400 */
402 {
403  union
404  {
405  struct
406  {
407  uint64 fvid : 5;
408  uint64 bcmd : 3;
409  uint64 resp : 3;
410  uint64 evnt0 : 3;
411  uint64 evnt1 : 3;
412  uint64 evnt2 : 3;
413  uint64 evnt3 : 3;
414  uint64 pbox_init_err : 1;
415  } fields; // nehalem-ex version
416  struct
417  {
418  uint64 fvid : 6;
419  uint64 bcmd : 3;
420  uint64 resp : 3;
421  uint64 evnt0 : 3;
422  uint64 evnt1 : 3;
423  uint64 evnt2 : 3;
424  uint64 evnt3 : 3;
425  uint64 pbox_init_err : 1;
426  } fields_wsm; // westmere-ex version
427  uint64 value;
428  };
429 };
430 
431 /* \brief Beckton Uncore PMU Counter Control Register format
432 
433  From "Intel(r) Xeon(r) Processor 7500 Series Uncore Programming Guide"
434  Table 2-67. M_MSR_PMU_CNT_CTL{5-0} Register - Field Definitions
435 */
437 {
438  union
439  {
440  struct
441  {
442  uint64 en : 1;
443  uint64 pmi_en : 1;
444  uint64 count_mode : 2;
445  uint64 storage_mode : 2;
446  uint64 wrap_mode : 1;
447  uint64 flag_mode : 1;
448  uint64 rsv1 : 1;
449  uint64 inc_sel : 5;
450  uint64 rsv2 : 5;
451  uint64 set_flag_sel : 3;
452  } fields;
453  uint64 value;
454  };
455 };
456 
457 /* \brief Sandy Bridge energy counters
458 */
459 
460 #define MSR_PKG_ENERGY_STATUS (0x611)
461 #define MSR_RAPL_POWER_UNIT (0x606)
462 #define MSR_PKG_POWER_INFO (0x614)
463 
464 #define PCM_INTEL_PCI_VENDOR_ID (0x8086)
465 #define PCM_PCI_VENDOR_ID_OFFSET (0)
466 
467 // server PCICFG uncore counters
468 
469 #define JKTIVT_MC0_CH0_REGISTER_DEV_ADDR (16)
470 #define JKTIVT_MC0_CH1_REGISTER_DEV_ADDR (16)
471 #define JKTIVT_MC0_CH2_REGISTER_DEV_ADDR (16)
472 #define JKTIVT_MC0_CH3_REGISTER_DEV_ADDR (16)
473 #define JKTIVT_MC0_CH0_REGISTER_FUNC_ADDR (4)
474 #define JKTIVT_MC0_CH1_REGISTER_FUNC_ADDR (5)
475 #define JKTIVT_MC0_CH2_REGISTER_FUNC_ADDR (0)
476 #define JKTIVT_MC0_CH3_REGISTER_FUNC_ADDR (1)
477 
478 #define JKTIVT_MC1_CH0_REGISTER_DEV_ADDR (30)
479 #define JKTIVT_MC1_CH1_REGISTER_DEV_ADDR (30)
480 #define JKTIVT_MC1_CH2_REGISTER_DEV_ADDR (30)
481 #define JKTIVT_MC1_CH3_REGISTER_DEV_ADDR (30)
482 #define JKTIVT_MC1_CH0_REGISTER_FUNC_ADDR (4)
483 #define JKTIVT_MC1_CH1_REGISTER_FUNC_ADDR (5)
484 #define JKTIVT_MC1_CH2_REGISTER_FUNC_ADDR (0)
485 #define JKTIVT_MC1_CH3_REGISTER_FUNC_ADDR (1)
486 
487 #define HSX_MC0_CH0_REGISTER_DEV_ADDR (20)
488 #define HSX_MC0_CH1_REGISTER_DEV_ADDR (20)
489 #define HSX_MC0_CH2_REGISTER_DEV_ADDR (21)
490 #define HSX_MC0_CH3_REGISTER_DEV_ADDR (21)
491 #define HSX_MC0_CH0_REGISTER_FUNC_ADDR (0)
492 #define HSX_MC0_CH1_REGISTER_FUNC_ADDR (1)
493 #define HSX_MC0_CH2_REGISTER_FUNC_ADDR (0)
494 #define HSX_MC0_CH3_REGISTER_FUNC_ADDR (1)
495 
496 #define HSX_MC1_CH0_REGISTER_DEV_ADDR (23)
497 #define HSX_MC1_CH1_REGISTER_DEV_ADDR (23)
498 #define HSX_MC1_CH2_REGISTER_DEV_ADDR (24)
499 #define HSX_MC1_CH3_REGISTER_DEV_ADDR (24)
500 #define HSX_MC1_CH0_REGISTER_FUNC_ADDR (0)
501 #define HSX_MC1_CH1_REGISTER_FUNC_ADDR (1)
502 #define HSX_MC1_CH2_REGISTER_FUNC_ADDR (0)
503 #define HSX_MC1_CH3_REGISTER_FUNC_ADDR (1)
504 
505 #define MC_CH_PCI_PMON_BOX_CTL_ADDR (0x0F4)
506 
507 #define MC_CH_PCI_PMON_FIXED_CTL_ADDR (0x0F0)
508 #define MC_CH_PCI_PMON_CTL3_ADDR (0x0E4)
509 #define MC_CH_PCI_PMON_CTL2_ADDR (0x0E0)
510 #define MC_CH_PCI_PMON_CTL1_ADDR (0x0DC)
511 #define MC_CH_PCI_PMON_CTL0_ADDR (0x0D8)
512 
513 #define MC_CH_PCI_PMON_FIXED_CTR_ADDR (0x0D0)
514 #define MC_CH_PCI_PMON_CTR3_ADDR (0x0B8)
515 #define MC_CH_PCI_PMON_CTR2_ADDR (0x0B0)
516 #define MC_CH_PCI_PMON_CTR1_ADDR (0x0A8)
517 #define MC_CH_PCI_PMON_CTR0_ADDR (0x0A0)
518 
519 #define JKTIVT_QPI_PORT0_REGISTER_DEV_ADDR (8)
520 #define JKTIVT_QPI_PORT0_REGISTER_FUNC_ADDR (2)
521 #define JKTIVT_QPI_PORT1_REGISTER_DEV_ADDR (9)
522 #define JKTIVT_QPI_PORT1_REGISTER_FUNC_ADDR (2)
523 #define JKTIVT_QPI_PORT2_REGISTER_DEV_ADDR (24)
524 #define JKTIVT_QPI_PORT2_REGISTER_FUNC_ADDR (2)
525 
526 #define HSX_QPI_PORT0_REGISTER_DEV_ADDR (8)
527 #define HSX_QPI_PORT0_REGISTER_FUNC_ADDR (2)
528 #define HSX_QPI_PORT1_REGISTER_DEV_ADDR (9)
529 #define HSX_QPI_PORT1_REGISTER_FUNC_ADDR (2)
530 #define HSX_QPI_PORT2_REGISTER_DEV_ADDR (10)
531 #define HSX_QPI_PORT2_REGISTER_FUNC_ADDR (2)
532 
533 #define QPI_PORT0_MISC_REGISTER_FUNC_ADDR (0)
534 #define QPI_PORT1_MISC_REGISTER_FUNC_ADDR (0)
535 #define QPI_PORT2_MISC_REGISTER_FUNC_ADDR (0)
536 
537 #define Q_P_PCI_PMON_BOX_CTL_ADDR (0x0F4)
538 
539 #define Q_P_PCI_PMON_CTL3_ADDR (0x0E4)
540 #define Q_P_PCI_PMON_CTL2_ADDR (0x0E0)
541 #define Q_P_PCI_PMON_CTL1_ADDR (0x0DC)
542 #define Q_P_PCI_PMON_CTL0_ADDR (0x0D8)
543 
544 #define Q_P_PCI_PMON_CTR3_ADDR (0x0B8)
545 #define Q_P_PCI_PMON_CTR2_ADDR (0x0B0)
546 #define Q_P_PCI_PMON_CTR1_ADDR (0x0A8)
547 #define Q_P_PCI_PMON_CTR0_ADDR (0x0A0)
548 
549 #define QPI_RATE_STATUS_ADDR (0x0D4)
550 
551 #define JKTIVT_PCU_MSR_PMON_CTR3_ADDR (0x0C39)
552 #define JKTIVT_PCU_MSR_PMON_CTR2_ADDR (0x0C38)
553 #define JKTIVT_PCU_MSR_PMON_CTR1_ADDR (0x0C37)
554 #define JKTIVT_PCU_MSR_PMON_CTR0_ADDR (0x0C36)
555 
556 #define JKTIVT_PCU_MSR_PMON_BOX_FILTER_ADDR (0x0C34)
557 
558 #define JKTIVT_PCU_MSR_PMON_CTL3_ADDR (0x0C33)
559 #define JKTIVT_PCU_MSR_PMON_CTL2_ADDR (0x0C32)
560 #define JKTIVT_PCU_MSR_PMON_CTL1_ADDR (0x0C31)
561 #define JKTIVT_PCU_MSR_PMON_CTL0_ADDR (0x0C30)
562 
563 #define JKTIVT_PCU_MSR_PMON_BOX_CTL_ADDR (0x0C24)
564 
565 #define HSX_PCU_MSR_PMON_CTR3_ADDR (0x071A)
566 #define HSX_PCU_MSR_PMON_CTR2_ADDR (0x0719)
567 #define HSX_PCU_MSR_PMON_CTR1_ADDR (0x0718)
568 #define HSX_PCU_MSR_PMON_CTR0_ADDR (0x0717)
569 
570 #define HSX_PCU_MSR_PMON_BOX_FILTER_ADDR (0x0715)
571 
572 #define HSX_PCU_MSR_PMON_CTL3_ADDR (0x0714)
573 #define HSX_PCU_MSR_PMON_CTL2_ADDR (0x0713)
574 #define HSX_PCU_MSR_PMON_CTL1_ADDR (0x0712)
575 #define HSX_PCU_MSR_PMON_CTL0_ADDR (0x0711)
576 
577 #define HSX_PCU_MSR_PMON_BOX_CTL_ADDR (0x0710)
578 
579 #define MC_CH_PCI_PMON_BOX_CTL_RST_CONTROL (1<<0)
580 #define MC_CH_PCI_PMON_BOX_CTL_RST_COUNTERS (1<<1)
581 #define MC_CH_PCI_PMON_BOX_CTL_FRZ (1<<8)
582 #define MC_CH_PCI_PMON_BOX_CTL_FRZ_EN (1<<16)
583 
584 #define UNCORE_PMON_BOX_CTL_VALID_BITS_MASK ((1<<17)-1)
585 
586 #define MC_CH_PCI_PMON_FIXED_CTL_RST (1<<19)
587 #define MC_CH_PCI_PMON_FIXED_CTL_EN (1<<22)
588 
589 #define MC_CH_PCI_PMON_CTL_EVENT(x) (x<<0)
590 #define MC_CH_PCI_PMON_CTL_UMASK(x) (x<<8)
591 #define MC_CH_PCI_PMON_CTL_RST (1<<17)
592 #define MC_CH_PCI_PMON_CTL_EDGE_DET (1<<18)
593 #define MC_CH_PCI_PMON_CTL_EN (1<<22)
594 #define MC_CH_PCI_PMON_CTL_INVERT (1<<23)
595 #define MC_CH_PCI_PMON_CTL_THRESH(x) (x<<24UL)
596 
597 #define Q_P_PCI_PMON_BOX_CTL_RST_CONTROL (1<<0)
598 #define Q_P_PCI_PMON_BOX_CTL_RST_COUNTERS (1<<1)
599 #define Q_P_PCI_PMON_BOX_CTL_RST_FRZ (1<<8)
600 #define Q_P_PCI_PMON_BOX_CTL_RST_FRZ_EN (1<<16)
601 
602 #define Q_P_PCI_PMON_CTL_EVENT(x) (x<<0)
603 #define Q_P_PCI_PMON_CTL_UMASK(x) (x<<8)
604 #define Q_P_PCI_PMON_CTL_RST (1<<17)
605 #define Q_P_PCI_PMON_CTL_EDGE_DET (1<<18)
606 #define Q_P_PCI_PMON_CTL_EVENT_EXT (1<<21)
607 #define Q_P_PCI_PMON_CTL_EN (1<<22)
608 #define Q_P_PCI_PMON_CTL_INVERT (1<<23)
609 #define Q_P_PCI_PMON_CTL_THRESH(x) (x<<24UL)
610 
611 #define PCU_MSR_PMON_BOX_FILTER_BAND_0(x) (x<<0)
612 #define PCU_MSR_PMON_BOX_FILTER_BAND_1(x) (x<<8)
613 #define PCU_MSR_PMON_BOX_FILTER_BAND_2(x) (x<<16)
614 #define PCU_MSR_PMON_BOX_FILTER_BAND_3(x) (x<<24)
615 
616 #define PCU_MSR_PMON_BOX_CTL_RST_CONTROL (1<<0)
617 #define PCU_MSR_PMON_BOX_CTL_RST_COUNTERS (1<<1)
618 #define PCU_MSR_PMON_BOX_CTL_FRZ (1<<8)
619 #define PCU_MSR_PMON_BOX_CTL_FRZ_EN (1<<16)
620 
621 #define PCU_MSR_PMON_CTL_EVENT(x) (x<<0)
622 #define PCU_MSR_PMON_CTL_OCC_SEL(x) (x<<14)
623 #define PCU_MSR_PMON_CTL_RST (1<<17)
624 #define PCU_MSR_PMON_CTL_EDGE_DET (1<<18)
625 #define PCU_MSR_PMON_CTL_EXTRA_SEL (1<<21)
626 #define PCU_MSR_PMON_CTL_EN (1<<22)
627 #define PCU_MSR_PMON_CTL_INVERT (1<<23)
628 #define PCU_MSR_PMON_CTL_THRESH(x) (x<<24UL)
629 #define PCU_MSR_PMON_CTL_OCC_INVERT (1UL<<30UL)
630 #define PCU_MSR_PMON_CTL_OCC_EDGE_DET (1UL<<31UL)
631 
632 
633 #define JKT_C0_MSR_PMON_CTR3 0x0D19 // CBo 0 PMON Counter 3
634 #define JKT_C0_MSR_PMON_CTR2 0x0D18 // CBo 0 PMON Counter 2
635 #define JKT_C0_MSR_PMON_CTR1 0x0D17 // CBo 0 PMON Counter 1
636 #define JKT_C0_MSR_PMON_CTR0 0x0D16 // CBo 0 PMON Counter 0
637 #define JKT_C0_MSR_PMON_BOX_FILTER 0x0D14 // CBo 0 PMON Filter
638 #define JKT_C0_MSR_PMON_CTL3 0x0D13 // CBo 0 PMON Control for Counter 3
639 #define JKT_C0_MSR_PMON_CTL2 0x0D12 // CBo 0 PMON Control for Counter 2
640 #define JKT_C0_MSR_PMON_CTL1 0x0D11 // CBo 0 PMON Control for Counter 1
641 #define JKT_C0_MSR_PMON_CTL0 0x0D10 // CBo 0 PMON Control for Counter 0
642 #define JKT_C0_MSR_PMON_BOX_CTL 0x0D04 // CBo 0 PMON Box-Wide Control
643 
644 #define JKTIVT_CBO_MSR_STEP 0x0020 // CBo MSR Step
645 
646 #define IVT_C0_MSR_PMON_BOX_FILTER1 0x0D1A // CBo 0 PMON Filter 1
647 
648 #define HSX_C0_MSR_PMON_CTR3 0x0E0B // CBo 0 PMON Counter 3
649 #define HSX_C0_MSR_PMON_CTR2 0x0E0A // CBo 0 PMON Counter 2
650 #define HSX_C0_MSR_PMON_CTR1 0x0E09 // CBo 0 PMON Counter 1
651 #define HSX_C0_MSR_PMON_CTR0 0x0E08 // CBo 0 PMON Counter 0
652 
653 #define HSX_C0_MSR_PMON_BOX_FILTER1 0x0E06 // CBo 0 PMON Filter1
654 #define HSX_C0_MSR_PMON_BOX_FILTER 0x0E05 // CBo 0 PMON Filter0
655 
656 #define HSX_C0_MSR_PMON_CTL3 0x0E04 // CBo 0 PMON Control for Counter 3
657 #define HSX_C0_MSR_PMON_CTL2 0x0E03 // CBo 0 PMON Control for Counter 2
658 #define HSX_C0_MSR_PMON_CTL1 0x0E02 // CBo 0 PMON Control for Counter 1
659 #define HSX_C0_MSR_PMON_CTL0 0x0E01 // CBo 0 PMON Control for Counter 0
660 
661 #define HSX_C0_MSR_PMON_BOX_STATUS 0x0E07 // CBo 0 PMON Box-Wide Status
662 #define HSX_C0_MSR_PMON_BOX_CTL 0x0E00 // CBo 0 PMON Box-Wide Control
663 
664 #define HSX_CBO_MSR_STEP 0x0010 // CBo MSR Step
665 
666 #define CBO_MSR_PMON_BOX_CTL_RST_CONTROL (1<<0)
667 #define CBO_MSR_PMON_BOX_CTL_RST_COUNTERS (1<<1)
668 #define CBO_MSR_PMON_BOX_CTL_FRZ (1<<8)
669 #define CBO_MSR_PMON_BOX_CTL_FRZ_EN (1<<16)
670 
671 #define CBO_MSR_PMON_CTL_EVENT(x) (x<<0)
672 #define CBO_MSR_PMON_CTL_UMASK(x) (x<<8)
673 #define CBO_MSR_PMON_CTL_RST (1<<17)
674 #define CBO_MSR_PMON_CTL_EDGE_DET (1<<18)
675 #define CBO_MSR_PMON_CTL_TID_EN (1<<19)
676 #define CBO_MSR_PMON_CTL_EN (1<<22)
677 #define CBO_MSR_PMON_CTL_INVERT (1<<23)
678 #define CBO_MSR_PMON_CTL_THRESH(x) (x<<24UL)
679 
680 #define JKT_CBO_MSR_PMON_BOX_FILTER_OPC(x) (x<<23UL)
681 #define IVTHSX_CBO_MSR_PMON_BOX_FILTER1_OPC(x) (x<<20UL)
682 
683 #define MSR_PACKAGE_THERM_STATUS (0x01B1)
684 #define MSR_IA32_THERM_STATUS (0x019C)
685 #define PCM_INVALID_THERMAL_HEADROOM ((std::numeric_limits<int32>::min)())
686 
687 #define MSR_DRAM_ENERGY_STATUS (0x0619)
688 
689 #define MSR_PKG_C2_RESIDENCY (0x60D)
690 #define MSR_PKG_C3_RESIDENCY (0x3F8)
691 #define MSR_PKG_C6_RESIDENCY (0x3F9)
692 #define MSR_PKG_C7_RESIDENCY (0x3FA)
693 #define MSR_CORE_C3_RESIDENCY (0x3FC)
694 #define MSR_CORE_C6_RESIDENCY (0x3FD)
695 #define MSR_CORE_C7_RESIDENCY (0x3FE)
696 
697 #ifdef _MSC_VER
698 #include <windows.h>
699 // data structure for converting two uint32s <-> uin64
700 union cvt_ds
701 {
702  UINT64 ui64;
703  struct
704  {
705  DWORD low;
706  DWORD high;
707  } ui32;
708 };
709 
710 #endif
711 
713 {
714  unsigned long long baseAddress;
715  unsigned short PCISegmentGroupNumber;
716  unsigned char startBusNumber;
717  unsigned char endBusNumber;
718  char reserved[4];
719  void print()
720  {
721  std::cout <<"BaseAddress="<< (std::hex) << "0x"<<baseAddress<< " PCISegmentGroupNumber=0x"<< PCISegmentGroupNumber <<
722  " startBusNumber=0x"<<(unsigned)startBusNumber<<" endBusNumber=0x" <<(unsigned)endBusNumber<< std::endl;
723  }
724 };
725 
727 {
728  char signature[4];
729  unsigned length;
730  unsigned char revision;
731  unsigned char checksum;
732  char OEMID[6];
733  char OEMTableID[8];
734  unsigned OEMRevision;
735  unsigned creatorID;
736  unsigned creatorRevision;
737  char reserved[8];
738 
739  unsigned nrecords() const
740  {
741  return (length - sizeof(MCFGHeader))/sizeof(MCFGRecord);
742  }
743 
744  void print()
745  {
746  std::cout << "Header: length="<<length<< " nrecords="<< nrecords() << std::endl;
747  }
748 };
749 
750 #endif
Definition: types.h:283
Definition: types.h:316
Definition: types.h:726
Definition: types.h:373
Definition: types.h:436
Definition: types.h:401
Definition: types.h:712