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Intel(r) Performance Counter Monitor
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Basic core counter state. More...
#include <cpucounters.h>
Public Member Functions | |
| BasicCounterState & | operator+= (const BasicCounterState &o) |
| int32 | getThermalHeadroom () const |
| Returns current thermal headroom below TjMax. | |
Protected Member Functions | |
| void | readAndAggregate (SafeMsrHandle *) |
Friends | |
| class | PCM |
| template<class CounterStateType > | |
| double | getExecUsage (const CounterStateType &before, const CounterStateType &after) |
| Computes average number of retired instructions per time intervall. More... | |
| template<class CounterStateType > | |
| double | getIPC (const CounterStateType &before, const CounterStateType &after) |
| Computes average number of retired instructions per core cycle (IPC) More... | |
| template<class CounterStateType > | |
| double | getAverageFrequency (const CounterStateType &before, const CounterStateType &after) |
| Computes average core frequency also taking Intel Turbo Boost technology into account. More... | |
| template<class CounterStateType > | |
| double | getActiveAverageFrequency (const CounterStateType &before, const CounterStateType &after) |
| Computes average core frequency when not in powersaving C0-state (also taking Intel Turbo Boost technology into account) More... | |
| template<class CounterStateType > | |
| double | getCyclesLostDueL3CacheMisses (const CounterStateType &before, const CounterStateType &after) |
| Estimates how many core cycles were potentially lost due to L3 cache misses. More... | |
| template<class CounterStateType > | |
| double | getCyclesLostDueL2CacheMisses (const CounterStateType &before, const CounterStateType &after) |
| Estimates how many core cycles were potentially lost due to missing L2 cache but still hitting L3 cache. More... | |
| template<class CounterStateType > | |
| double | getRelativeFrequency (const CounterStateType &before, const CounterStateType &after) |
| Computes average core frequency also taking Intel Turbo Boost technology into account. More... | |
| template<class CounterStateType > | |
| double | getActiveRelativeFrequency (const CounterStateType &before, const CounterStateType &after) |
| Computes average core frequency when not in powersaving C0-state (also taking Intel Turbo Boost technology into account) More... | |
| template<class CounterStateType > | |
| double | getL2CacheHitRatio (const CounterStateType &before, const CounterStateType &after) |
| Computes L2 cache hit ratio. More... | |
| template<class CounterStateType > | |
| double | getL3CacheHitRatio (const CounterStateType &before, const CounterStateType &after) |
| Computes L3 cache hit ratio. More... | |
| template<class CounterStateType > | |
| uint64 | getL3CacheMisses (const CounterStateType &before, const CounterStateType &after) |
| Computes number of L3 cache misses. More... | |
| template<class CounterStateType > | |
| uint64 | getL2CacheMisses (const CounterStateType &before, const CounterStateType &after) |
| Computes number of L2 cache misses. More... | |
| template<class CounterStateType > | |
| uint64 | getL2CacheHits (const CounterStateType &before, const CounterStateType &after) |
| Computes number of L2 cache hits. More... | |
| template<class CounterStateType > | |
| uint64 | getL3CacheOccupancy (const CounterStateType &now) |
| Computes L3 Cache Occupancy. More... | |
| template<class CounterStateType > | |
| uint64 | getCycles (const CounterStateType &before, const CounterStateType &after) |
| Computes the number core clock cycles when signal on a specific core is running (not halted) More... | |
| template<class CounterStateType > | |
| uint64 | getInstructionsRetired (const CounterStateType &before, const CounterStateType &after) |
| Computes the number of retired instructions. More... | |
| template<class CounterStateType > | |
| uint64 | getCycles (const CounterStateType &now) |
| Computes the number executed core clock cycles. More... | |
| template<class CounterStateType > | |
| uint64 | getInstructionsRetired (const CounterStateType &now) |
| Computes the number of retired instructions. More... | |
| template<class CounterStateType > | |
| uint64 | getL3CacheHitsNoSnoop (const CounterStateType &before, const CounterStateType &after) |
| Computes number of L3 cache hits where no snooping in sibling L2 caches had to be done. More... | |
| template<class CounterStateType > | |
| uint64 | getL3CacheHitsSnoop (const CounterStateType &before, const CounterStateType &after) |
| Computes number of L3 cache hits where snooping in sibling L2 caches had to be done. More... | |
| template<class CounterStateType > | |
| uint64 | getL3CacheHits (const CounterStateType &before, const CounterStateType &after) |
| Computes total number of L3 cache hits. More... | |
| template<class CounterStateType > | |
| uint64 | getNumberOfCustomEvents (int32 eventCounterNr, const CounterStateType &before, const CounterStateType &after) |
| Returns the number of occured custom core events. More... | |
| template<class CounterStateType > | |
| uint64 | getInvariantTSC (const CounterStateType &before, const CounterStateType &after) |
| Computes number of invariant time stamp counter ticks. More... | |
| template<class CounterStateType > | |
| uint64 | getRefCycles (const CounterStateType &before, const CounterStateType &after) |
| Computes the number of reference clock cycles while clock signal on the core is running. More... | |
| template<class CounterStateType > | |
| double | getCoreCStateResidency (int state, const CounterStateType &before, const CounterStateType &after) |
| Computes residency in the core C-state. More... | |
Basic core counter state.
Intended only for derivation, but not for the direct use
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Computes average core frequency when not in powersaving C0-state (also taking Intel Turbo Boost technology into account)
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes average core frequency when not in powersaving C0-state (also taking Intel Turbo Boost technology into account)
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes average core frequency also taking Intel Turbo Boost technology into account.
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes residency in the core C-state.
| state | C-state |
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes the number core clock cycles when signal on a specific core is running (not halted)
Returns number of used cycles (halted cyles are not counted). The counter does not advance in the following conditions:
The performance counter for this event counts across performance state transitions using different core clock frequencies
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes the number executed core clock cycles.
Returns number of used cycles (halted cyles are not counted).
| now | Current CPU counter state |
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Estimates how many core cycles were potentially lost due to missing L2 cache but still hitting L3 cache.
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Estimates how many core cycles were potentially lost due to L3 cache misses.
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes average number of retired instructions per time intervall.
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes the number of retired instructions.
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes the number of retired instructions.
| now | Current CPU counter state |
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Computes number of invariant time stamp counter ticks.
This counter counts irrespectively of C-, P- or T-states
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes average number of retired instructions per core cycle (IPC)
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes L2 cache hit ratio.
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes number of L2 cache hits.
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes number of L2 cache misses.
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes L3 cache hit ratio.
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes total number of L3 cache hits.
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes number of L3 cache hits where no snooping in sibling L2 caches had to be done.
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes number of L3 cache hits where snooping in sibling L2 caches had to be done.
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes number of L3 cache misses.
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes L3 Cache Occupancy.
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Returns the number of occured custom core events.
Read number of events programmed with the CUSTOM_CORE_EVENTS
| eventCounterNr | Event/counter number (value from 0 to 3) |
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes the number of reference clock cycles while clock signal on the core is running.
The reference clock operates at a fixed frequency, irrespective of core frequency changes due to performance state transitions. See Intel(r) Software Developer's Manual for more details
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
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Computes average core frequency also taking Intel Turbo Boost technology into account.
| before | CPU counter state before the experiment |
| after | CPU counter state after the experiment |
1.8.7